Event Date
A brief overview of the present understanding of tradeoff between Energy and Errors in Computing will be presented. There is a large body of research that claims that a tradeoff exists between energy and accuracy of computing. The basis of such claims comes from the understanding of a chip’s behavior under large Process Variations with statistical delay assumptions. It leads one to conclude that a small number of errors are likely as we lower the supply voltage to save energy. This understanding is challenged by the speaker with his new hypothesis on the behavior of large CMOS chips in the presence of process variations. A Thought Experiment is presented which leads to the new hypothesis. The new hypothesis states that in every large CMOS chip, there exist Critical Operations Points (Frequency, Voltage) such that it divides the 2-D space (F, V) into two distinct spaces: 1. Error-free operation and 2. Massive number of Errors (i.e., completely inoperable). Two attempts at disproving this hypothesis with real physical experiments will be described. The conclusion reached is that Energy-Accuracy tradeoff is not possible in microprocessor sized chips. But the good news is that we can save energy by lowering Voltage down to Critical Voltage and not worry about an error occurring.
Janak H. Patel is a Donald Biggar Wilett Professor Emeritus of Engineering and a Research Professor in Department of Electrical and Computer Engineering at University of Illinois at Urbana-Champaign.
Patel’s research contributions include Pipeline Scheduling, Cache Coherence, Cache Simulation, Cache Prefetching, Interconnection Networks, On-line Error Detection, Reliability analysis of memories with ECC and scrubbing, Design for Testability, Built-In Self-Test, Fault Simulation and Automatic Test Generation. Patel has supervised over 85 M.S. and Ph.D. theses and published over 200 technical papers. He was a founding technical advisor to Nexgen Microsystems that gave rise to the entire line of microprocessors from AMD. He was a founder of successful startup, Sunrise Test, a CAD company for chip testing, now owned by Synopsys.
He received a Bachelor of Science (1967) degree in Physics from Gujarat University, India, and Bachelor of Technology (1970) in Electrical Engineering from the Indian Institute of Technology, Madras, India, and a Master of Science and Ph.D. (1976) in Electrical Engineering from Stanford University. He is a Fellow of ACM (2001) and IEEE (1989) and a recipient of the 1998 IEEE Piore Award. He received a Lifetime Contribution Medal from the IEEE Test Technology Council in 2016.